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etrontech em638165 etron technology, inc. no. 6, technology rd. v, hsinchu science park, hsinchu, taiwan 30078, r.o.c. tel: (886)-3-5782345 fax: (886)-3-5778671 etron technology, inc. reserves the right to change products or specific ation without notice. 4m x 16 bit synchronous dram (sdram) preliminary (rev. 5.3, dec. /2013) features ? fast access time from clock: 4.5/5.4/5.4 ns ? fast clock rate: 200/166/143 mhz ? fully synchronous operation ? internal pipelined architecture ? 1m word x 16-bit x 4-bank ? programmable mode registers - cas latency: 2 or 3 - burst length: 1, 2, 4, 8, or full page - burst type: sequential or interleaved - burst stop function - optional drive strength control ? auto refresh and self refresh ? 4096 refresh cycles/64ms ? cke power down mode ? single +3.3v 0.3v power supply ? operating temperature: ta = 0~70c ? interface: lvttl ? 54-pin 400 mil plastic tsop ii package - pb and halogen free ? 54-ball 8.0 x 8.0 x 1.2mm (max) fbga package - pb free and halogen free table1. key specifications table 2. ordering information h: indicates pb free and halogen free overview the em638165 sdram is a high-speed cmos synchronous dram containing 64 mbits. it is internally configured as 4 banks of 1m word x 16 dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). read and write accesses to the sdram are burst oriented; accesses st art at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of a bank activate command which is then followed by a read or write command. the em638165 provides for programmable read or write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the refresh functions, either auto or self refresh are easy to use. by having a programmable mode register, the system can choose the most suitable modes to maximize its performance. these devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance pc applications. em638165 - 5/6/7 tck3 clock cycle time(min.) 5/6/7 ns tac3 access time from clk(max.) 4.5/5.4/5.4 ns tras row active time(min.) 40/42/42 ns trc row cycle time(min.) 55/60/63 ns part number frequency package em638165ts -5g 200mhz tsop ii em638165ts -6g 166mhz tsop ii em638165ts -7g 143mhz tsop ii em638165bm -5h 200mhz fbga em638165bm -6h 166mhz fbga em638165bm -7h 143mhz fbga ts: indicates tsopii package bm: indicates fbga package g: indicates pb and halogen free for tsopii package
etrontech em638165 rev. 5.3 2 dec. /2013 figure 1. pin assignment (top view) 154 vdd vss 253 dq0 dq15 352 vddq vssq 451 dq1 dq14 550 dq2 dq13 649 vssq vddq 748 dq3 dq12 847 dq4 dq11 946 vddq vssq 10 45 dq5 dq10 11 44 dq6 dq9 12 43 vssq vddq 13 42 dq7 dq8 14 41 vdd vss 15 40 ldqm nc/rfu 16 39 we# udqm 17 38 cas# clk 18 37 ras# cke 19 36 cs# nc 20 35 ba0 a11 21 34 ba1 a9 22 33 a10/ap a8 23 32 a0 a7 24 31 a1 a6 25 30 a2 a5 26 29 a3 a4 27 28 vdd vss figure 2. ball assignment (top view) ? 12 78 a b c d e f g h j 3 vss dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 nc udqm clk nc a11 a8 a7 vss a5 vssq vddq vssq vddq vss cke a9 a6 a4 vddq dq0 vssq dq2 vddq dq4 vssq dq6 vdd ldqm cas# ras# ba0 ba1 a0 a1 a3 a2 vdd dq1 dq3 dq5 dq7 we# cs# a10 vdd 9
etrontech em638165 rev. 5.3 3 dec. /2013 figure 3. block diagram clk cke cs# ras# cas# we# clock buffer command decoder column counter control signal generator refresh counter dq buffer 1m x 16 cell array (bank #a) row decoder 1m x 16 cell array (bank #b) row decoder 1m x 16 cell array (bank #c) row decoder 1m x 16 cell array (bank #d) row decoder column decoder column decoder column decoder column decoder mode register a9 a11 ba0 ba1 ~ a0 dq15 dq0 ~ address buffer a10/ap ldqm, udqm
etrontech em638165 rev. 5.3 4 dec. /2013 pin descriptions table 3. pin details of em638165 symbol type description clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also in crements the internal burst counter and controls the output registers. cke input clock enable: cke activates (high) and deactivates (low) the clk signal. if cke goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended fr om the next clock cy cle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating t he clock controls the entry to the power down and self refresh modes. cke is sy nchronous except after the device enters power down and self refresh modes, where cke becomes asynchronous until exiting the same mode. the input buffe rs, including clk, are disabled during power down and self refresh modes, providing low standby power. ba0,ba1 input bank activate: ba0, ba1 input select the bank for operation. ba1 ba0 select bank 0 0 bank #a 0 1 bank #b 1 0 bank #c 1 1 bank #d a0-a11 input address inputs: a0- a 11 are sampled during the bankactivate command (row address a0-a11) and read/write command (column address a0- a 7 with a10 defining auto precharge) to select one lo cation out of the 1m available in the respective bank. during a precharge command, a10 is sampled to determine if all banks are to be precharged (a10 = high). the address inputs also provide the op-code during a mode register set command. cs# input chip select: cs# enables (sampled low) and di sables (sampled high) the command decoder. all commands are masked when cs# is sampled high. cs# provides for external bank selection on systems with multiple banks. it is considered part of the command code. ras# input row address strobe: the ras# signal defines the operation commands in conjunction with the cas# and we# signals and is latched at the positive edges of clk. when ras# and cs# are asserted "low" and cas# is asserted "high," either the bankactivate command or t he precharge command is selected by the we# signal. when the we# is asserted "h igh," the bankactivate command is selected and the bank designated by ba is tu rned on to the active state. when the we# is asserted "low," the precharge command is selected and the bank designated by ba is switched to the idle state after the precharge operation. cas# input column address strobe: the cas# signal defines the operation commands in conjunction with the ras# and we# signals and is latched at the positive edges of clk. when ras# is held "high" and cs# is asserted "low," the column access is started by asserting cas# "low." then, the read or write command is selected by asserting we# "low" or "high." we# input write enable: the we# signal defines the operation commands in conjunction with the ras# and cas# signals and is la tched at the positive edges of clk. the we# input is used to select the bank activate or precharge command and read or write command.
etrontech em638165 rev. 5.3 5 dec. /2013 ldqm, udqm input data input/output mask: controls output buffers in read mode and masks input data in write mode. dq0-dq15 input / output data i/o: the dq0-15 input and output data are synchronized with the positive edges of clk. the i/os are maskable during reads and writes. nc/rfu - no connect: these pins should be left unconnected. v ddq supply dq power: provide isolated power to dqs for improved noise immunity. ( 3.3v 0.3v ) v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. ( 0 v ) v dd supply power supply: +3.3v 0.3v v ss supply ground
etrontech em638165 rev. 5.3 6 dec. /2013 operation mode fully synchronous operations are performed to latch t he commands at the positive edges of clk. table 4 shows the truth table for the operation commands. table 4. truth table (note (1), (2)) command state cke n-1 cke n dqm ba 0,1 a 10 a 0-9,11 cs# ras# cas# we# bankactivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) h x v v l column address (a0 ~ a7) l h l l write and autoprecharge active (3) h x v v h l h l l read active (3) h x v v l column address (a0 ~ a7) l h l h read and autoprecharge active (3) h x v v h l h l h mode register set idle h x x op code l l l l extended mode register set idle h x x op code l l l l no-operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x (selfrefresh) l h h h clock suspend mode entry active h l x x x x h x x x l v v v power down mode entry any (5) h l x x x x h x x x l h h h clock suspend mode exit active l h x x x x x x x x power down mode exit any l h x x x x h x x x (powerdown) l h h h data write/output enable active h x l x x x x x x x data mask/output disable active h x h x x x x x x x note: 1. v=valid, x=don't care l=low level h=high level 2. cke n signal is input level when commands are provided. cke n-1 signal is input level one clock cycl e before the commands are provided. 3. these are states of bank designated by ba signal. 4. device state is 1, 2, 4, 8, and full page burst operation. 5. power down mode can not enter in the burst operation. when this command is asserted in the bur st cycle, device state is clock suspend mode.
etrontech em638165 rev. 5.3 7 dec. /2013 commands 1 bankactivate (ras# = "l", cas# = "h", we# = "h ", bas = bank, a0-a11 = row address) the bankactivate command activates the idle bank designated by the ba0, 1 signal. by latching the row address on a0 to a11 at the time of this command, t he selected row access is initiated. the read or write operation in the same bank can occur after a time delay of t rcd (min.) from the time of bank activation. a subsequent bankactivate command to a different ro w in the same bank can only be issued after the previous active row has been precharged (refer to t he following figure). the minimum time interval between successive bankactivate commands to the same bank is defined by t rc (min.). the sdram has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to- back activation of the two banks. t rrd (min.) specifies the minimum time required between activating different banks. after this command is used, the write command and the block write command perform the no mask write operation. clk command t0 t1 address t2 t3 tn+3 tn+4 tn+5 tn+6 ras# - cas# delay(t rcd ) ras# - ras# delay time(t rrd ) ras# - cycle time(t rc ) autoprecharge begin bank a row addr. bank a col addr. bank b row addr. bank a row addr. bank a activate nop nop r/w a with autoprecharge bank b activate nop nop bank a activate don?t care figure 4. bankactivate command cycle (burst length = n) 2 bankprecharge command (ras# = "l", cas# = "h", we# = "l", bas = bank, a10 = "l", a0-a9 and a11 = don't care) the bankprecharge command precharges the bank designated by ba signal. the precharged bank is switched from the active state to the idle st ate. this command can be asserted anytime after t ras (min.) is satisfied from the bankactivate command in t he desired bank. the maximum time any bank can be active is specified by t ras (max.). therefore, the precharge functi on must be performed in any active bank within t ras (max.). at the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. 3 prechargeall command (ras# = "l", cas# = "h", we# = "l", bas = d on?t care, a10 = "h", a0-a9 and a11 = don't care) the prechargeall command precharges all banks simu ltaneously and can be issued even if all banks are not in the active state. all banks ar e then switched to the idle state. 4 read command (ras# = "h", cas# = "l", we# = "h", bas = bank, a10 = "l", a0-a7 = column address) the read command is used to read a burst of data on c onsecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the read command is issued. during read bursts, the valid data-out elem ent from the starting column address will be available following the cas latency after the issue of the read command. each subsequent data-out element will be valid by the next positive clock edge (refer to the following fi gure). the dqs go into high-impedance at the end of the burst unless other command is initiated. the burst length, burst sequence, and cas latency are determined by the mode register, which is already programmed. a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue.
etrontech em638165 rev. 5.3 8 dec. /2013 clk command t0 t1 t2 t3 t4 t5 t6 read a nop nop nop nop nop nop nop t7 t8 nop cas# latency=2 t ck2 , dq cas# latency=3 t ck3 , dq dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 figure 5. burst read operation (burst length = 4, cas# latency = 2, 3) the read data appears on the dqs subject to the val ues on the dqm inputs two clocks earlier (i.e. dqm latency is two clocks for output buffers). a r ead burst without the auto precharge function may be interrupted by a subsequent read or write command to the same bank or the other active bank before the end of the burst length. it may be interrupted by a bankprecharge/ prechargeall command to the same bank too. the interrupt coming from the r ead command can occur on any clock cycle following a previous read command (refer to the following figure). clk command t0 t1 t2 t3 t4 t5 t6 read a read b nop nop nop nop nop nop t7 t8 nop cas# latency=2 t ck2 , dq cas# latency=3 t ck3 , dq dout a 0 dout b 0 dout b 1 dout b 2 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout b 3 figure 6. read interrupted by a read (burst length = 4, cas# latency = 2, 3) the dqm inputs are used to avoid i/o contention on t he dq pins when the interrupt comes from a write command. the dqms must be asserted (high) at least two clocks prior to the write command to suppress data-out on the dq pins. to guarantee the dq pins against i/o contention, a single cycle with high-impedance on the dq pins must occur between t he last read data and the write command (refer to the following three figures). if the data output of the burst read occurs at the second clock of the burst write, the dqms must be asserted (high) at least one clock prior to the write command to avoid internal bus contention. clk command t0 t1 t2 t3 t4 t5 t6 nop nop bank a activate nop nop read a write a nop t7 t8 nop cas# latency=2 t ck2 , dq dqm t9 nop din a 0 din a 1 din a 2 din a 3 figure 7. read to write interval (burst length 4, cas# latency = 2)
etrontech em638165 rev. 5.3 9 dec. /2013 clk command t0 t1 t2 t3 t4 t5 t6 nop read a nop nop nop nop write b nop t7 t8 nop dqm dout a 0 din b 0 din b 1 din b 2 cas# latency=3 t ck3 , dq must be hi-z before the write command don?t care figure 8. read to write interval (burst length 4, cas# latency = 3) clk command t0 t1 t2 t3 t4 t5 t6 nop nop read a nop nop write b nop nop t7 t8 nop dqm din b 0 din b 1 din b 2 din b 3 cas# latency=2 t ck2 , dq must be hi-z before the write command don?t care figure 9. read to write interval (burst length 4, cas# latency = 2) a read burst without the auto precharge function ma y be interrupted by a bankprecharge/ prechargeall command to the same bank. the following figure s hows the optimum time that bankprecharge/ prechargeall command is issued in different cas latency. clk command t0 t1 t2 t3 t4 t5 t6 read a nop nop nop precharge nop nop activate t7 t8 nop cas# latency=2 t ck2 , dq cas# latency=3 t ck3 , dq dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 address bank, col a bank (s) bank row t rp figure 10. read to precharge (cas# latency = 2, 3) 5 read and autoprecharge command (ras# = "h", cas# = "l", we# = "h", bas = bank, a10 = "h", a0-a7 = column address) the read and autoprecharge command automatically performs the precharge operation after the read operation. once this command is given, any subs equent command cannot occur within a time delay of {t rp (min.) + burst length}. at full-page burst, only the read operation is performed in this command and the auto precharge function is ignored.
etrontech em638165 rev. 5.3 10 dec. /2013 6 write command (ras# = "h", cas# = "l", we# = "l", bas = bank, a10 = "l", a0-a7 = column address) the write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the write command is issued. during write bursts, the first valid data-in element will be regist ered coincident with the wri te command. subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). the dqs remain with high-impedance at the end of the burst unl ess another command is initia ted. the burst length and burst sequence are determined by the mode register, wh ich is already programmed. a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). clk dq t0 t1 t2 t3 t4 t5 t6 din a 0 din a 1 din a 2 din a 3 don?t care t7 t8 command nop write a nop nop nop nop nop nop nop the first data element and the write are registered on the same clock edge figure 11. burst write operation (burst length = 4) a write burst without the auto precharge func tion may be interrupted by a subsequent write, bankprecharge/prechargeall, or read co mmand before the end of the burst l ength. an interrupt coming from write command can occur on any clock cycle following the previous write command (refer to the following figure). clk dq t0 t1 t2 t3 t4 t5 t6 din a 0 din b 0 din b 1 din b 2 din b 3 t7 t8 command nop write a write b nop nop nop nop nop nop figure 12. write interrupted by a write (burst length = 4) the read command that interrupts a write burst wit hout auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. in order to avoid data contention, input data must be removed from the dqs at least one clo ck cycle before the first read data appears on the outputs (refer to the following figure). once the read comm and is registered, the data inputs will be ignored and writes will not be executed. clk command t0 t1 t2 t3 t4 t5 t6 nop write a read b nop nop nop nop nop t7 t8 nop cas# latency=2 t ck2 , dq cas# latency=3 t ck3 , dq dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 din a 0 don?t care din a 0 don?t care don?t care input data must be removed from the dq at least one clock cycle before the read data appears on the outputs to avoid data contention figure 13. write interrupted by a read (burst length = 4, cas# latency = 2, 3)
etrontech em638165 rev. 5.3 11 dec. /2013 the bankprecharge/prechargeall command that interrupts a write burst without t he auto precharge function should be issued m cycles after the clock edge in which the la st data-in element is registered, where m equals t wr /t ck rounded up to the next whole number. in addition, t he dqm signals must be used to mask input data, starting with the clock edge following the last data- in element and ending with the clock edge on which the bankprecharge/prechargeall command is ent ered (refer to the following figure). clk command t0 t1 t2 t3 t4 t5 t6 write nop nop precharge nop nop activate nop t7 dqm don?t care address bank col n bank (s) row t rp din n din n+1 t wr dq note: the ldqm/udqm can remain low in this example if the length of the write burst is 1 or 2. figure 14. write to precharge 7 write and autoprecharge command (ras# = "h", cas# = "l", we# = "l", bas = bank, a10 = "h", a0-a7 = column address) the write and autoprecharge command performs the pr echarge operation automatically after the write operation. once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + t wr + t rp (min.)}. at full-page burst, only the wr ite operation is performed in this command and the auto precharge function is ignored. clk dq t0 t1 t2 t3 t4 t5 t6 din a 0 din a 1 t7 t8 command bank a activate nop nop write a auto precharge nop nop nop nop nop t9 bank a activate t dal =t wr +t rp t dal begin autoprecharge bank can be reactivated at completion of t dal figure 15. burst write with auto-precharge (burst length = 2) 8 mode register set command (ras# = "l", cas# = "l", we# = "l", a0-a11 = register data) the mode register stores the data for controlling the various operating modes of sdram. the mode register set command programs the values of c as latency, addressing mode and burst length in the mode register to make sdram useful for a variety of different applications. the default values of the mode register after power-up are undefined; theref ore this command must be issued at the power-up sequence. the state of pins a0~a9 and a11 in the same cycle is the data written to the mode register. two clock cycles are required to complete the write in the mode register (refer to the following figure). the contents of the mode register can be c hanged using the same command and the clock cycle requirements during operation as long as all banks are in the idle state.
etrontech em638165 rev. 5.3 12 dec. /2013 table 5. mode register bitmap ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 rfu* 0 rfu* wbl test mode cas latency bt burst length a9 write burst length a8 a7 test mode a3 burst type 0 burst 0 0 normal 0 sequential 1 single bit 1 0 vendor use only 1 interleave 0 1 vendor use only a6 a5 a4 cas latency a2 a1 a0 burst length 0 0 0 reserved 0 0 0 1 0 0 1 reserved 0 0 1 2 0 1 0 2 clocks 0 1 0 4 0 1 1 3 clocks 0 1 1 8 1 0 0 reserved 1 1 1 full page (sequential) all other reserved all other reserved *note: rfu (reserved for future use) should stay ?0? during mrs cycle. clk cs# t0 t1 t2 t3 t4 t5 t6 t7 cke don?t care ras# t mrd cas# t8 t9 t10 we# ba0,1 a10 a0-a9, a11 dqm dq t rp prechargeall mode register set command any command hi-z address key figure 16. mode register set cycle
etrontech em638165 rev. 5.3 13 dec. /2013 ? burst length field (a2~a0) this field specifies the data length of column a ccess using the a2~a0 pins and selects the burst length to be 2, 4, 8, or full page. table 6. burst length field a2 a1 a0 burst length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 full page ? burst type field (a3) the burst type can be one of two modes, interleave mode or sequential mode. table 7. burst type field a3 burst type 0 sequential 1 interleave ? burst definition, addressing sequenc e of sequential and interleave mode table 8. burst definition burst length start address sequential interleave a2 a1 a0 2 x x 0 0, 1 0, 1 x x 1 1, 0 1, 0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 full page location = 0-255 n, n+1, n+2, n+3, ?255, 0, 1, 2, ? n-1, n, ? not support
etrontech em638165 rev. 5.3 14 dec. /2013 ? cas latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read command to the first read whole value satisfying the following formula must be programmed into this field. t cac (min) cas latency x t ck table 9. cas latency field a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 x x reserved ? test mode field (a8~a7) these two bits are used to enter the test mode and must be programmed to "00" in normal operation. table 10. test mode field a8 a7 test mode 0 0 normal mode 0 1 vendor use only 1 x vendor use only ? write burst length (a9) this bit is used to select the write burst mode. w hen the a9 bit is "0", the burst-read-burst-write mode is selected. when the a9 bit is "1", t he burst-read-single-write mode is selected. table 11. write burst length a9 write burst mode 0 burst-read-burst-write 1 burst-read-single-write note: a10 and ba0, 1 should stay ?l? during mode set cycle. ? extended mode register bitmap table 12.extended mode register bitmap ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 0 0 0 0 0 0 0 0 0 0 ds 0 extended mode register a1 drive strength 0 full 1 weak
etrontech em638165 rev. 5.3 15 dec. /2013 9 no-operation command (ras# = "h", cas# = "h", we# = "h") the no-operation command is used to perform a nop to the sdram which is selected (cs# is low). this prevents unwanted commands from being r egistered during idle or wait states. 10 burst stop command (ras# = "h", cas# = "h", we# = "l") the burst stop command is used to terminate either fixed-length or full-page bursts. this command is only effective in a read/write burst without the auto precharge functi on. the terminated read burst ends after a delay equal to the cas latency (refer to the fo llowing figure). the termination of a write burst is shown in the following figure. clk command t0 t1 t2 t3 t4 t5 t6 read a nop nop nop burst stop nop nop nop t7 t8 nop cas# latency=2 t ck2 , dq cas# latency=3 t ck3 , dq dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 the burst ends after a delay equal to the cas# latency figure 17 . termination of a burst read operation ( burst length 4, cas# latency = 2, 3) clk dq t0 t1 t2 t3 t4 t5 t6 din a 0 din a 1 din a 2 don?t care t7 t8 command nop write a nop nop burst stop nop nop nop nop figure 18. termination of a burst write operation (burst length = x) 11 device deselect command (cs# = "h") the device deselect command disables the co mmand decoder so that the ras#, cas#, we# and address inputs are ignored, regardle ss of whether the clk is enabled. th is command is similar to the no operation command. 12 autorefresh command (ras# = "l", cas# = "l", we# = "h", cke = "h", a0-a11 = don't care) the autorefresh command is used during normal oper ation of the sdram and is analogous to cas#- before-ras# (cbr) refresh in conventional drams . this command is non-persistent, so it must be issued each time a refresh is required. the addressi ng is generated by the internal refresh controller. this makes the address bits a "don't care" during an autorefresh command. the internal refresh counter increments automatically on every aut o refresh cycle to all of the rows. the refresh operation must be performed 4096 times within 64ms. the time required to complete the auto refresh operation is specified by t rc (min.). to provide the autorefresh command, a ll banks need to be in the idle state and the device must not be in power down mode (cke is high in the previous cycle). this command must be followed by nops until the auto refresh operation is comp leted. the precharge time requirement, t rp (min), must be met before successive auto refresh operations are performed.
etrontech em638165 rev. 5.3 16 dec. /2013 13 selfrefresh entry command (ras# = "l", cas# = "l", we# = "h", cke = "l", a0-a11 = don't care) the selfrefresh is another refresh mode available in the sdram. it is the preferred refresh mode for data retention and low power operation. once the self refresh command is registered, all the inputs to the sdram become "don't care" with the exception of cke, which must remain low. the refresh addressing and timing is internally generated to reduce power consumption. the sdram may remain in selfrefresh mode for an indefinite period. the selfrefr esh mode is exited by rest arting the external clock and then asserting high on cke (selfrefresh exit command). 14 selfrefresh exit command this command is used to exit from the selfrefres h mode. once this command is registered, nop or device deselect commands must be issued for t xsr (min.) because time is required for the completion of any bank currently being internally refreshed. if auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refres h cycles should be completed just prior to entering and just after exiting the selfrefresh mode. 15 clock suspend mode entry / powerdown mode entry command (cke = "l") when the sdram is operating the bur st cycle, the internal clk is suspended (masked) from the subsequent cycle by issuing this command (asserting cke "low"). the device operation is held intact while clk is suspended. on the other hand, when all ban ks are in the idle state, this command performs entry into the powerdown mode. a ll input and output buffers (except the cke buffer) are turned off in the powerdown mode. the device may not remain in the clock suspend or powerdown state longer than the refresh period (64ms) since the comm and does not perform any refresh operations. 16 clock suspend mode exit / powerdown mode exit command (cke= "h") when the internal clk has been suspended, the operation of the internal clk is reinitiated from the subsequent cycle by providing this command (asse rting cke "high", the command should be nop or deselect). when the device is in the powerdown mode, the device exits this mode and all disabled buffers are turned on to the active state. t pde (min.) is required when the device exits from the powerdown mode. any subsequent commands can be iss ued after one clock cycle from the end of this command. 17 data write / output enable, data mask / output disable command (dqm = "l", "h") during a write cycle, the dqm signal functions as a data mask and can control every word of the input data. during a read cycle, the dqm functions as the controller of out put buffers. dqm is also used for device selection, byte selection and bus control in a memory system.
etrontech em638165 rev. 5.3 17 dec. /2013 table 13. absolute maximum rating symbol item - 5/6/7 unit note v in , v out input, output voltage - 1.0 ~ 4.6 v 1 v dd , v ddq power supply voltage -1.0 ~ 4.6 v 1 t a ambient temperature 0 ~ 70 c 1 t stg storage temperature - 55 ~ 150 c 1 p d power dissipation 1 w 1 i os short circuit output current 50 ma 1 table 14. recommended d.c. operating conditions (t a = 0~70c) symbol parameter min. typ. max. unit note v dd power supply voltage 3.0 3.3 3.6 v 2 v ddq power supply voltage(for i/o buffer) 3.0 3.3 3.6 v 2 v ih lvttl input high voltage 2.0 ? v ddq +0.3 v 2 v il lvttl input low voltage - 0.3 ? 0.8 v 2 i il input leakage current ( 0v v in v dd , all other pins not under test = 0v ) - 10 ? 10 a i ol output leakage current output disable, 0v v out v ddq ) - 10 ? 10 a v oh lvttl output "h" level voltage ( i out = -2ma ) 2.4 ? ? v v ol lvttl output "l" level voltage ( i out = 2ma ) ? ? 0.4 v table 15. capacitance (v dd = 3.3v, f = 1mhz, t a = 25c) symbol parameter min. max. unit c i input capacitance 1 4 pf c i/o input/output capacitance 2 5 pf note: these parameters are periodica lly sampled and are not 100% tested.
etrontech em638165 rev. 5.3 18 dec. /2013 table 16. d.c. characteristics (v dd = 3.3v 0.3v, t a = 0~70c) description/test condition symbol -5 -6 -7 unit note max. operating current t rc t rc (min), outputs open one bank active i dd1 55 50 45 ma 3 precharge standby current in non-power down mode t ck = 15ns, cs# v ih (min), cke v ih input signals are changed every 2clks i dd2n 20 20 20 precharge standby current in non-power down mode t ck = , clk v il (max), cke v ih i dd2ns 12 12 12 precharge standby current in power down mode t ck = 15ns, cke v il (max) i dd2p 2 2 2 precharge standby current in power down mode t ck = , cke v il (max) i dd2ps 2 2 2 active standby current in non-power down mode t ck = 15ns, cke v ih (min), cs# v ih (min) input signals are changed every 2clks i dd3n 30 30 30 active standby current in non-power down mode cke v ih (min), clk v il (max), t ck = i dd3ns 25 25 25 operating current (burst mode) t ck =t ck (min), outputs open, multi-bank interleave i dd4 80 75 70 3, 4 refresh current t rc t rc (min) i dd5 65 60 55 3 self refresh current cke 0.2v ; for other inputs vih vdd - 0.2v, vil 0.2v i dd6 2 2 2
etrontech em638165 rev. 5.3 19 dec. /2013 table 17. electrical characteristics a nd recommended a.c. operating conditions (v dd = 3.3v ? 0.3v, t a = 0~70c) (note: 5, 6, 7, 8) symbol a.c. parameter -5 -6 -7 unit note min. max. min. max. min. max. t rc row cycle time (same bank) 55 - 60 - 63 - ns t rcd ras# to cas# delay (same bank) 15 - 18 - 21 - t rp precharge to refresh/row activate command (same bank) 15 - 18 - 21 - t rrd row activate to row activate delay (different banks) 10 - 12 - 14 - t ras row activate to precharge time (same bank) 40 100k 42 100k 42 100k t wr write recovery time 2 - 2 - 2 - t ck t ccd cas# to cas# delay time 1 - 1 - 1 - t ck clock cycle time cl* = 2 - - 9 - 10 - ns 9 cl* = 3 5 - 6 - 7 - t ch clock high time 2 - 2.5 - 2.5 - 10 t cl clock low time 2 - 2.5 - 2.5 - 10 t ac access time from clk (positive edge) cl* = 2 - - - 6 - 6 10 cl* = 3 - 4.5 - 5.4 - 5.4 t oh data output hold time 2 - 2.5 - 2.5 - 9 t lz data output low impedance 0 - 0 - 0 - t hz data output high impedance - 4.5 - 5.4 - 5.4 8 t is data/address/control input set-up time 1.5 - 1.5 - 1.5 - 10 t ih data/address/control input hold time 0.8 - 0.8 - 0.8 - 10 t pde power down exit set-up time t is +t ck - t is +t ck - t is+ t ck - t mrd mode register set command cycle time 2 - 2 - 2 - t ck t refi average refresh interval time - 15.6 - 15.6 - 15.6 s t xsr exit self-refresh to any command t rc +t is - t rc +t is - t rc+ t is - ns cl is cas latency note: 1. stress greater than those list ed under "absolute maximum ratings" may cause permanent damage to the device. 2. all voltages are referenced to v ss . vih (max) = 4.6v for pulse width 3ns. vil(min) = -1.0v for pulse width 3ns. 3. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during every 2 t ck. 4. these parameters depend on the out put loading. specified values are obtained with the output open. 5. power-up sequence is described in note 11. 6. a.c. test conditions
etrontech em638165 rev. 5.3 20 dec. /2013 table 18. lvttl interface reference level of output signals 1.4v / 1.4v output load reference to the under output load (b) input signal levels 2.4v / 0.4v transition time (rise and fall) of input signals 1ns reference level of input signals 1.4v output 1.2k ? 30pf 3.3v 870 ? output z0=50 ? 50 ? 30pf 1.4v figure 19.1 lvttl d.c. test load (a) figure 19.2 lvttl a.c. test load (b) 7. transition times are measured between v ih and v il . transition (rise and fall) of input signals are in a fixed slope (1 ns). 8. t hz defines the time in which the outputs achieve the open circuit conditi on and are not at reference levels. 9. if clock rising time is longer than 1 ns, ( t r / 2 -0.5) ns should be added to the parameter. 10. assumed input rise and fall time t t ( t r & t f ) = 1 ns if t r or t f is longer than 1 ns, transient time compensation shoul d be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 11. power up sequence power up must be performed in the following sequence. 1) power must be applied to v dd and v ddq (simultaneously) when cke= ?l?, dqm= ?h? and all input signals are held "nop" state . 2) start clock and maintain stable condition for minimum 200 s, then bring cke= ?h? and, it is recommended that dqm is held "high" (v dd levels) to ensure dq output is in high impedance. 3) all banks must be precharged. 4) extended mode register set command and mode regi ster set command must be asserted to initialize the mode register. 5) a minimum of 2 auto-refresh dummy cycles must be required to stabilize the internal circuitry of the device. * the auto refresh command can be issue before or after mode register set command
etrontech em638165 rev. 5.3 21 dec. /2013 timing waveforms figure 20. ac parameters for write timing (burst length=4) t0 t1 t2 don?t care t ch activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t cl begin auto precharge bank b rax rbx ray rax cax rbx cbx ray cay ax0 ax1 ax2 ax3 bx0 bx1 bx2 bx3 ay0 ay1 ay2 ay3 t rcd t rc t dal t wr write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write command bank a precharge command bank a t is t is t ih t ih t is begin auto precharge bank a t is t ih hi-z clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq
etrontech em638165 rev. 5.3 22 dec. /2013 figure 21. ac parameters for read timing (burst length=2, cas# latency=2) hi-z clk cs# t0 t1 t2 cke don?t care ras# t ch cas# we# ba0,1 a10 a0-a9, a11 dqm dq activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t cl begin auto precharge bank b rax rbx rax cax rbx cbx ray ray ax0 ax1 t rrd t rc read command bank a activate command bank b read with auto precharge command bank b activate command bank a t is t ih t ih t is t is t ih t ras t rcd t ac t lz t hz bx0 bx1 t hz t rp precharge command bank a t oh
etrontech em638165 rev. 5.3 23 dec. /2013 figure 22. auto refresh (burst length=4, cas# latency=2) t0 t1 t2 don?t care precharge all command t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax cax rax ax0 ax1 t rp t rc auto refresh command auto refresh command activate command bank a read command bank a t rc t rcd clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq
etrontech em638165 rev. 5.3 24 dec. /2013 figure 23. power on sequence and auto refresh hi-z t0 t1 t2 don?t care inputs must be stable for 200s t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t mrd extended mode register set command high level is reguired minimum for 2 refresh cycles are required t rp precharge all command 1st auto refresh (*) command 2nd auto refresh (*) command any command note (*) : the auto refresh command can be issue before or after mode register set command clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq address key mode register set command t mrd ba0=h ba1=l ba0=l ba1=l
etrontech em638165 rev. 5.3 25 dec. /2013 figure 24. self refresh entry & exit cycle clk cs# t0 t1 t2 cke don?t care ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq self refresh entry t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 self refresh exit auto refresh t is hi-z t is t ih *note 1 *note 2 *note 3,4 t pde *note 5 *note 6 *note 7 t xsr *note 8 hi-z *note 9 note: to enter selfrefresh mode 1. cs#, ras# & cas# with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including the system clock c an be don't care except for cke. 3. the device remains in selfrefres h mode as long as cke stays "low". 4. once the device enters selfrefresh mode, minimum t ras is required before exit from selfrefresh. to exit selfrefresh mode 5. system clock restart and be st able before returning cke high. 6. enable cke and cke should be set high for valid setup time and hold time. 7. cs# starts from high. 8. minimum t xsr is required after cke going high to complete selfrefresh exit. 9. 4096 cycles of burst autorefresh is required before self refresh entry and after selfrefresh exit if the system uses burst refresh.
etrontech em638165 rev. 5.3 26 dec. /2013 figure 25.1. clock suspension during burst read (using cke) (burst length=4, cas# latency=2) hi-z t0 t1 t2 don?t care t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax rax cax activate command bank a read command bank a ax0 ax1 ax2 ax3 t hz clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq
etrontech em638165 rev. 5.3 27 dec. /2013 figure 25.2. clock suspension during burst read (using cke) (burst length=4, cas# latency=3) hi-z t0 t1 t2 don?t care t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax rax cax activate command bank a read command bank a ax0 ax1 ax2 ax3 t hz clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq
etrontech em638165 rev. 5.3 28 dec. /2013 figure 26. clock suspension during burst write (using cke) (burst length=4) hi-z t0 t1 t2 don?t care t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax rax cax activate command bank a write command bank a clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq dax0 dax1 dax2 dax3
etrontech em638165 rev. 5.3 29 dec. /2013 figure 27. power down mode and clock suspension (burst length=4, cas# latency=2) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t is power down mode exit t pde power down mode entry read command bank a clock suspension start power down mode exit t ih rax rax cax ax0 ax1 ax3 ax2 active standby clock suspension end precharge command bank a power down mode entry precharge standby any command valid t hz clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq
etrontech em638165 rev. 5.3 30 dec. /2013 figure 28.1. random column read (page within same bank) (burst length=4, cas# latency=2) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a raw raw cax aw0 aw1 ay2 precharge command bank a clk raz caw cay raz caz aw2 aw3 ax0 ax1 ay0 ay1 ay3 az0 read command bank a read command bank a activate command bank a read command bank a cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq
etrontech em638165 rev. 5.3 31 dec. /2013 figure 28.2. random column read (page within same bank) (burst length=4, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a raw raw cax aw0 aw1 ay2 precharge command bank a clk raz caw cay raz caz aw2 aw3 ax0 ax1 ay0 ay1 ay3 read command bank a read command bank a activate command bank a read command bank a cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq
etrontech em638165 rev. 5.3 32 dec. /2013 figure 29. random column write (page within same bank) (burst length=4) hi-z t0 t1 t2 don?t care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank b rbw rbw cbx dbw0 dbw1 dby2 precharge command bank b clk rbz cbw cby rbz cbz dbw2 dbw3 dbx0 dbx1 dby0 dby1 dby3 write command bank b write command bank b activate command bank b write command bank b cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq dbz0 dbz1
etrontech em638165 rev. 5.3 33 dec. /2013 figure 30.1. random row r ead (interleaving banks) (burst length=8, cas# latency=2) hi-z t0 t1 t2 don?t care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank b rbx rbx rax bx0 bx1 ax0 precharge command bank b clk rby cbx cax rby cby bx2 bx3 bx4 bx5 bx6 bx7 ax1 activate command bank a read command bank a activate command bank b read command bank b cs# cke we# a10 ax6 ax7 high rax ax2 ax3 ax4 ax5 t rcd t ac t rp a0-a9, a11 dqm dq ba0,1 ras# cas#
etrontech em638165 rev. 5.3 34 dec. /2013 figure 30.2. random row r ead (interleaving banks) (burst length=8, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank b rbx rbx rax bx0 bx1 ax0 precharge command bank b clk rby cbx cax rby cby bx2 bx3 bx4 bx5 bx6 bx7 ax1 activate command bank a read command bank a activate command bank b read command bank b cs# cke we# a10 ax6 ax7 high rax ax2 ax3 ax4 ax5 t rcd t ac t rp a0-a9, a11 dqm dq ba0,1 ras# cas# precharge command bank a by0
etrontech em638165 rev. 5.3 35 dec. /2013 figure 31. random row writ e (interleaving banks) (burst length=8) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank a rax rax rbx dax3 dax4 dbx3 precharge command bank a clk ray cax cbx ray cay dax5 dax6 dax7 dbx0 dbx1 dbx2 dbx4 activate command bank b write command bank b activate command bank a write command bank a cs# cke we# a10 day1 day2 high rbx dbx5 dbx6 dbx7 day0 t rcd t rp a0-a9, a11 dqm dq ba0,1 ras# cas# precharge command bank b day3 t wr* t wr* dax0 dax1 dax2 *t wr >t wr (min.)
etrontech em638165 rev. 5.3 36 dec. /2013 figure 32.1. read and write cycle (burst length=4, cas# latency=2) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax day1 clk cax caz ax0 ax1 ax2 ax3 day0 write command bank a the write data is masked with a zero clock latency read command bank a the read data is masked with a two clock latency cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq az1 az3 cay day3 az0
etrontech em638165 rev. 5.3 37 dec. /2013 figure 32.2. read and write cycle (burst length=4, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax day1 clk cax caz ax0 ax1 ax2 ax3 day0 write command bank a the write data is masked with a zero clock latency read command bank a the read data is masked with a two clock latency cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq az1 az3 cay day3 az0
etrontech em638165 rev. 5.3 38 dec. /2013 figure 33.1. interleaving column read cycle (burst length=4, cas# latency=2) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax rbx ax0 ax1 by0 read command bank a clk rbx cay cbw ax2 ax3 bw0 bw1 bx0 bx1 by1 activate command bank b read command bank b read command bank b precharge command bank b cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq bz2 bz3 cbx cby cay cbz t rcd t ac read command bank b read command bank b bz0 ay0 ay1 bz1 precharge command bank a
etrontech em638165 rev. 5.3 39 dec. /2013 figure 33.2. interleaved column read cycle (burst length=4, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax rbx ax0 ax1 bz0 precharge command bank b clk rbx cax cbx ax2 ax3 bx0 bx1 by0 by1 bz1 activate command bank b read command bank b precharge command bank a cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq cby cbz cay t rcd t ac read command bank b read command bank a ay2 ay0 ay1 ay3 read command bank b
etrontech em638165 rev. 5.3 40 dec. /2013 figure 34. interleaved column write cycle (burst length=4) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank a rax rax rbw dax0 dax1 dby0 write command bank b clk rbw cax cbw dax2 dax3 dbw0 dbw1 dbx0 dbx1 dby1 activate command bank b write command bank b precharge command bank a cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq cbx cby cay t rcd write command bank b write command bank a dbz0 day0 day1 dbz1 write command bank b cbz t rrd >t rrd (min) t wr t wr dbz2 dbz3 precharge command bank b
etrontech em638165 rev. 5.3 41 dec. /2013 figure 35.1. auto precharge after read burst (burst length=4, cas# latency=2) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax cbx ax0 ax1 bx0 read with auto precharge command bank a clk raz cax cay rby cby ax2 ax3 bx1 activate command bank b read with auto precharge command bank b activate command bank b activate command bank a cs# cke we# a10 ay2 ay3 high rbx bx2 bx3 ay0 ay1 t rp a0-a9, a11 dqm dq ba0,1 ras# cas# rby rbx raz by2 by0 by1 read with auto precharge command bank b begin auto precharge bank b begin auto precharge bank a
etrontech em638165 rev. 5.3 42 dec. /2013 figure 35.2. auto precharge after read burst (burst length=4, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax rbx bx2 rbx cax cbx ax0 ax1 ax2 ax3 bx0 bx1 bx3 activate command bank b read with auto precharge command bank a read with auto precharge command bank b cay activate command bank b ay2 ay0 ay1 ay3 read with auto precharge command bank b rby t rp begin auto precharge bank b begin auto precharge bank a rby cby by2 by0 by1 clk cs# cke ras# cas# we# ba0,1 a10 a0-a9, a11 dqm dq high
etrontech em638165 rev. 5.3 43 dec. /2013 figure 36. auto precharge after write burst (burst length=4) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank a rax rax rbx dbx2 rbx cax cbx dax0 dax1 dax2 dax3 dbx0 dbx1 dbx3 activate command bank b write with auto precharge command bank a write with auto precharge command bank b cay activate command bank b day2 day0 day1 day3 write with auto precharge command bank b rby t dal begin auto precharge bank b begin auto precharge bank a rby cby dby2 dby0 dby1 clk cs# cke we# ba0,1 a10 dqm dq high dby3 ras# cas# a0-a9, a11
etrontech em638165 rev. 5.3 44 dec. /2013 figure 37.1. full page read cycle (burst length=full page, cas# latency=2) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax ax+1 rbx cax rbx ax ax+1 ax+2 ax-2 ax-1 ax bx activate command bank b read command bank b precharge command bank b cbx burst stop command bx+3 bx+1 bx+2 bx+4 the burst counter wraps from the highest order page address back to zero during this time interval t rp rby rby bx+5 bx+6 clk cs# cke we# a10 dq high full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address activate command bank b ras# cas# ba0,1 a0-a9, a11 dqm
etrontech em638165 rev. 5.3 45 dec. /2013 figure 37.2. full page read cycle (burst length=full page, cas# latency=3) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax ax+1 rbx cax rbx ax ax+1 ax+2 ax-2 ax-1 ax bx activate command bank b read command bank b precharge command bank b cbx burst stop command bx+3 bx+1 bx+2 bx+4 the burst counter wraps from the highest order page address back to zero during this time interval t rp rby rby bx+5 clk cs# cke we# a10 dq high full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address activate command bank b ras# cas# ba0,1 a0-a9, a11 dqm
etrontech em638165 rev. 5.3 46 dec. /2013 figure 38. full page write cycle (burst length=full page) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 write command bank a rax rax dax+1 rbx cax rbx dax dax+1 dax+2 dax+3 dax-1 dax dbx activate command bank b write command bank b precharge command bank b cbx burst stop command dbx+3 dbx+1 dbx+2 dbx+4 the burst counter wraps from the highest order page address back to zero during this time interval rby rby dbx+5 clk cs# cke we# a10 dq high full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address activate command bank b ras# cas# ba0,1 a0-a9, a11 dqm data is ignored
etrontech em638165 rev. 5.3 47 dec. /2013 figure 39. byte read and write operation (burst length=4, cas# latency=2) t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read command bank a rax rax cax upper byte is masked write command bank a lower byte is masked cay read command bank a lower byte is masked caz clk cs# cke we# a10 dq8-dq15 high lower byte is masked ras# cas# ba0,1 a0-a9, a11 ldqm udqm ax0 ax1 ax2 day1 day2 az1 az2 dq0-dq7 ax1 ax2 ax3 day0 day3 day1 az0 az1 az2 az3 upper byte is masked
etrontech em638165 rev. 5.3 48 dec. /2013 figure 40. random row read (interleaving banks) (burst length=4, cas# latency=2) t0 t1 t2 don?t care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read bank b with auto precharge rbu rbu rau bv0 rau cbu cau bu0 bu1 bu2 bu3 au0 au1 bv1 activate command bank a activate command bank b read bank a with auto precharge rbv activate command bank a av0 bv2 bv3 av1 read bank a with auto precharge cbv t rp begin auto precharge bank a begin auto precharge bank b rav cav clk cs# cke we# a10 dqm dq high begin auto precharge bank b begin auto precharge bank a rbw rbv rav rbw t rp t rp read bank b with auto precharge au2 au3 av2 av3 activate command bank b ras# cas# ba0,1 a0-a9, a11
etrontech em638165 rev. 5.3 49 dec. /2013 figure 41. full page random column read (burst length=full page, cas# latency=2) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 activate command bank b rax cax by1 rbx rbx cay ax0 ax1 bx0 ay0 ay1 by0 az0 read command bank a read command bank b precharge command bank b (precharge temination) caz read command bank a bz0 az1 az2 bz1 read command bank a cbz t rp rbw rbw bz2 clk cs# cke ras# cas# we# a10 dqm dq rax cbx cby t rrd t rcd read command bank b read command bank b activate command bank b ba0,1 a0-a9, a11
etrontech em638165 rev. 5.3 50 dec. /2013 figure 42. full page random column write (burst length=full page) hi-z t0 t1 t2 don?t care activate command bank a t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 activate command bank b rax cax dby1 rbx rbx cay dax0 dax1 dbx0 day0 day1 dby0 daz0 write command bank a write command bank b precharge command bank b (precharge temination) caz write command bank a dbz0 daz1 daz2 dbz1 write command bank a cbz t rp rbw rbw dbz2 clk cs# cke ras# cas# we# a10 dqm dq rax cbx cby t rrd t rcd write command bank b write command bank b activate command bank b ba0,1 a0-a9, a11 t wr write data are masked
etrontech em638165 rev. 5.3 51 dec. /2013 figure 43. precharge termination of a burst (burst length=4, 8 or full page, cas# latency=3) t0 t1 t2 don?t care activate command bank b t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 rax rax ay0 cax dax0 dax1 ay1 write command bank a activate command bank a activate command bank a ray precharge command bank a ay2 precharge command bank a cay t wr raz clk cs# cke we# a10 dqm dq high raz ray t rp read command bank a precharge termination of a read burst t rp precharge termination of a write burst write data are masked a0-a9, a11 ras# cas# ba0,1
etrontech em638165 rev. 5.3 52 dec. /2013 figure 44. 54 pin tsop ii package outline drawing information symbol dimension in inch dimension in mm min nom max min nom max a --- --- 0.047 --- --- 1.2 a1 0.002 --- 0.008 0.05 --- 0.2 a2 0.035 0.039 0.043 0.9 1.0 1.1 b 0.01 0.014 0.018 0.25 0.35 0.45 c 0.004 0.006 0.008 0.12 0.165 0.21 d 0.87 0.875 0.88 22.09 22.22 22.35 e 0.395 0.400 0.405 10.03 10.16 10.29 e --- 0.031 --- --- 0.8 --- he 0.455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.02 0.024 0.4 0.5 0.6 l1 0.032 --- --- 0.84 --- s --- 0.028 --- --- 0.71 --- y --- --- 0.004 --- --- 0.1 0 --- 8 0 --- 8 notes: 1. dimension d&e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. dimension s includes end flash. 4. controlling dimension: mm
etrontech em638165 rev. 5.3 53 dec. /2013 figure 45. 54 ball tfbga package outline drawing information top view bottom view side view a1 index symbol dimension in inch dimension in mm min nom max min nom max a -- -- 0.047 -- -- 1.20 a1 0.010 0.012 0.014 0.25 0.30 0.35 a2 -- 0.033 -- -- 0.85 -- d 0.311 0.315 0.319 7.90 8.00 8.10 e 0.311 0.315 0.319 7.90 8.00 8.10 d1 -- 0.252 -- -- 6.40 -- e1 -- 0.252 -- -- 6.40 -- e -- 0.031 -- -- 0.80 -- b 0.016 0.018 0.020 0.40 0.45 0.50 f -- 0.126 -- -- 3.20 --

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